The semiconductor industry is built on

complexity. Every node, every

generation, every new packaging

technique adds another layer of

interdependence between design tools, IP

providers, and foundries that need to

move in lockstep just to keep progress

on schedule. Today, that means there are

thousands of companies each optimized

for different parts of the chip design

and manufacturing process. We're talking

the hardware, the software, the IP, the

tools, and everything in between. Each

of these segments also has multiple

players, making it an interesting

dynamic from the foundry point of view.

For example, today's video sponsor,

TSMC, has an open ecosystem of players

that are both partners and competitors.

It creates an interesting mix when it

comes to standardizing the process top

to bottom. This time, TSMC has invited

me to explore how its open innovation

platform ecosystem, also called OIP,

operates together both with TSMC and its

key players. And we traveled through a

full-day visit to six key partners in

Silicon Valley. These partners include

Alchip, GUC, Siemens, Cadence, Synopsys,

and Analog Bits.

>> [gasps]

>> All whose span across chip design

services, EDA, and IP.

So, we approached the day with a simple

question. The goal of this channel is

for me to provide you, the audience,

with more information about the chip

industry, because at times it's a

complex web of wafers, IP, packaging,

and go-to-market slide decks.

I wanted to ask a simple question. How

does this actually work?

What keeps all these companies moving in

the roughly the same direction when the

technology changes so fast and the

stakes are so high?

What exactly does collaboration mean in

an industry that competes this hard?

So, over the next 20 minutes or so,

you'll hear from the people who live

inside that tension, who have to share

roadmaps, align tool chains, and somehow

keep secrets at the same time.

Now, this is the quieter side of the

semiconductor business, but it's the

reason why progress doesn't grind to a

halt.

>> Hi, I'm Shankar Krishnamoorthy, Chief

Product Development Officer at Synopsys,

and I'd like to welcome you Ian to

Synopsys.

>> Hi, I'm Paul Cunningham,

senior vice president and general

manager of the system verification group

at Cadence. Welcome.

>> Uh my name is Steve Wang. I'm the

general manager of Alchip North America.

>> Hi, my name is Aditya Raina. I am the

CMO at GUC,

and we'd like to welcome TSMC to GUC.

>> Uh my name is Juan Rey. Uh I am the

senior vice president and general

manager for Calibre

at Siemens Electronic Design Automation.

Welcome to Siemens.

>> Hello, my name is Mahesh Tripathi. I'm

CEO of Analog Bits. Please welcome to

Analog Bits.

>> Yeah, I think we're in a very exciting

phase of technology innovation.

Um

I think when you look at the whole AI

buildout that is happening around us,

it's really driving

uh just a rigorous pace across every

layer of the technology stack. You see

AI companies are trying to essentially

release chips almost every 18 months or

so, and that is putting a tremendous

pressure on the entire uh design flow

from verification to implementation to

process development, manufacturing in

order to keep up with that pace. So,

it's really an exciting time for the

industry, tremendous innovation

happening across every layer of the the

stack, and of course great results

uh in terms of the systems that are

getting rolled out as part of the AI

buildout.

>> So, I think so but you know, the given

that the scale of the market is is so

large, I mean that that if you like that

NRE, that upfront cost is is far

outweighed by the benefit of enabling

more and more of this accelerated or

custom computing. Uh

I think the costs I mean, they are

larger, but on the other hand,

you know, you look at the ecosystem that

we created with EDA and of course

foundries and and close foundry partners

like TSMC

uh and also IP and the building blocks

around it. So, we've actually made it it

relatively low cost and actually really,

really predictable. I mean, especially

what what TSMC have accomplished in

advanced manufacturing and packaging.

That that predictability has been

absolutely instrumental to saying,

"Look, we really can have a world of

accelerated custom computing."

>> Uh from my perspective uh

because the whole industry is now moved

to this 18-month or or shorter rhythm,

it means uh that Synopsys has to

innovate much, much faster than ever

before. And so, our development cycles

have also become incredibly fast. And we

are also benefiting from uh technologies

like AI to accelerate that whole

development uh cycle.

>> This kind of compression of schedules

um I think it's one of the biggest

challenges we're all facing together.

It's also one of the greatest

opportunities. So,

um

you know, we were privileged that uh

we had an annual, you know, our annual

customer event earlier this year

uh and there was a talk there from from

Google. Um and they they they made what

kind of actually you think about it is

kind of an obvious observation that if

you look end-to-end uh a traditional

silicon cycle from conceiving of an

architecture, going through architecture

design, RTL design, implementation,

sign-off, and then actually waiting of

course for the wafers back from the fab,

you're looking at like 2 and 1/2,

sometimes 3 years end-to-end.

Um

during that whole process, if you if

you're looking at accelerating AI, every

6 months you've you've a new model. Yep.

got a new uh

technology coming out from the software

side. So, so by the time that silicon is

actually, you know, into mass

production, you're like 2 and 1/2, you

know, 2 and 1/2 years out of date. So,

this view of can you actually deliver a

chip every 6 months even?

Uh you know, that could be

transformative and goes back to your

point that you might say, "Well, how on

earth could you make the NRE, the

upfront cost?"

But, the scale of the market, if you've

got hundreds of billions of dollars,

trillions, I mean, the forecast for the

semiconductor industry by

2030 now is already 1.25 trillion,

right? And it's and it's still rising.

So,

given the costs and and our ability to

automate, you know, actually, it makes

sense it can make economic sense to do a

chip every 6 months in some of these

industries.

But, we yeah, how are we going to do it?

Cuz, you know, 6 months would have to

include time in the fab. Yep. So,

everything's got to come down. And

that's probably like, you know, 3 months

of of

design cycle and 3 months in the fab.

So, anyway, it's it's an exciting time,

you know, for sure.

>> Oh, it's a

>> It's very important cuz we already uh

started No, 3 nanometer

uh you know, uh generation for us,

right? It's past. And now we're working

on the many designs starting with the 2

nanometer. Actually, we have like uh

three or four customer projects ongoing

with the 2 nanometer uh taping out like

uh even toward the end of the year. And

then we of course, you know, we have a

uh multiple projects in taping out next

year.

>> Mhm.

>> [clears throat]

>> Yeah.

>> Well, it changes it in in in multiple

ways. Um

first of all, um

the concept of putting everything in uh

a system on a chip, on a single

uh device, uh essentially um

defines a series of technical

requirements for the system. When

thinking on

going into a third direction, into a

third dimension, it is necessary to now

um um

disaggregate the systems in a way that

they can still communicate with a

performance and bandwidth that it is

required

um to achieve those those higher goals.

So, there are multiple technical

requirements

and

uh one of the incredible things that is

happening is that there is a diversity

of solutions now that are being offered

to the ultimate customer

that

um

address different types of niche needs

in different market areas. And all that

requires a very comprehensive view,

high-level view on how to um deliver

solutions that that work for for those

customers.

>> Um in terms of power delivery, it's

changed quite a bit because most of our

customers now need to have proper

thermal regulation not only voltage but

also thermal regulation in in terms of

how they can manage heat between these

chips. Uh most of our customers are

stacking the dies, so they also want

chiplet-like interfaces. So, we built

custom chip-to-chip interfaces for our

customers. Um so, managing

thermal clocking and also ability to get

external chips onto the onto one

substrate is very important. So, those

are some of the challenges that

customers are facing and we're solving

it for them.

>> So,

the the uh introduction of CoWoS and 3D

has been pretty much a game changer in

terms of uh how much compute you can

provide. So, on the 2.5D, GUC has very

strong SI and PI capabilities. We work

very closely with TSMC on uh developing

IP on CoWoS technologies.

3D GUC was one of the very first

companies to jump onto the 3D shuttle

that TSMC provided. And now we consider

ourselves to be leaders in 3D

technology.

So, overall, we think closer

collaboration with TSMC has enabled UMC

to learn these technologies earlier

and develop a flow that eventually

provides customers with an optimal set

of tools and technologies to play with.

>> You know, I look at

the overall theme of energy efficiency

of AI, right? I mean, essentially, in

the AI world, the key metric that

everybody's optimizing for is dollars

per million tokens and watts per million

tokens. And there's a certain

trajectory that that needs to go down at

for all of this stuff to make sense.

And, you know, partnerships like ours

with TSMC are really key to making that

trajectory to get realized. And I see

advanced packaging and 3D IC as an

integral technology to enable that

energy efficiency vision to come to

reality. As you move more and more

dies, which were on a on a PCB earlier,

onto the same package, you're

essentially dramatically improving the

energy efficiency of that function. And

one of the things we are super excited

about is our partnership around 3D

fabric and the 3D blocks

approach to designing advanced packages,

where essentially, literally in maybe 3

years of work,

we are now we pretty much have every

aspect of that PCB completely integrated

in a single package, including the

voltage regulator, which is the most

recent innovation to roll out. And so,

these things, along with co-packaged

optics, are all huge steps that have

been taken to drive that energy

efficiency direction amongst over and

above everything we're doing with

respect to rolling out the 2 nanometer

nodes and the A16 super power rail or

the A14 next generation

gate all around process. So, all these

are just kind of an all of the above

strategy to attack that energy

efficiency problem.

>> There is always a need. There is

absolutely

no way to fulfill the the the solutions

today that

they would like to have in 5 years, 10

years, 20 years from now. So, the amount

of creativity, fortunately, that this

industry overall has is is is really

very reassuring, very refreshing.

Um and yes, there are there are absolute

needs.

You can see on on the on the needs

coming from multiple communities.

Right now, it is very clear that

hyperscaling,

AI, that type of applications

are being addressed as the most

immediate need.

Um the market is growing tremendously in

that space.

But then, you see in pretty much any

community, it doesn't matter if you're

looking into

microcontrollers or if you're looking

into

the defense, aerospace, and military

type of applications. If you look into

the type of

radiation hard type of applications that

the industry needs for communications.

Uh

you can see that each one of those areas

have a specific niche need for 3D. And

each one of them drives multiple

different vectors and directions that

need to be addressed.

>> You know, I think that the very AI that

we are choosing to enable with all this

work that we are doing together is also

going to cause a tremendous disruption

in the tools and technologies we are

delivering to our user community. I'm

super excited about the direction we are

taking in AI going from reinforcement

learning to LLM-based EDA to now agentic

AI. And I expect that the whole workflow

for silicon engineering, system

engineering to get disrupted

significantly with a genetic workflows.

And that's going to open up R&D capacity

in a significant way, which is going to

enable more chips to get designed, more

systems to get designed. And so I see

this as this positive feedback loop

>> Okay.

>> where essentially you open up more

capacity that drives more innovation,

which helps the whole

AI

progress to go even faster. So that's a

a really exciting phenomenon to watch.

Yeah, you know, because

the pace of innovation has picked up so

much. In the past,

typically our work with TSMC would start

around 0.5 PDK, and then we would work

together, get all the flows ready, the

design platform ready, and then the

customers would come, move to the

platform, and the chip would get

delivered in 3 years. Now, all that

essentially got compressed by at least

2x or more. And so our work with TSMC

starts very early in terms of

pathfinding.

>> Mhm.

>> The customer joins that collaboration

much, much earlier than ever before. And

that's the only way we can keep up with

this this rigorous pace that's been set

for the evolution of

silicon for the AI buildout.

>> TSMC has been a very important a partner

in the OIP platform, right? We are one

of the

platform partners, right? OIP partner.

And you know, we also have to leverage a

lot of other, you know, partners in TSMC

in order to build the chips. The EDAs,

IP,

advanced packages, you know,

hybrid and hybrid with memories, HBMs,

you know,

SK Hynix and Samsung. They all they are

all part of TSMC ecosystem. We work with

We work around the ecosystem. Without

the ecosystem, we just can't build the

chips.

>> Do Do you find that there a lot There's

a lot more effort, a lot more partners

involved just to go from design to

delivery?

>> Uh yes, um in terms of

uh

the design itself, we work very

collaboratively with the EDA companies.

Um so, Synopsys, Cadence, ANSYS, uh and

Mentor

are some of the common companies that we

work with. So, there's a lot of

collaboration with them in terms of how

accurately can we design these building

blocks and how accurately they model

them. TSMC has done a nice job by having

these flows certified, so it helps us

jump-start very quickly. But, there's

always some things that we can we give

them feedback on improvement on

accuracy.

That's one part of the second part of

the chain is also in qualifying it on

silicon.

>> Mhm.

>> So, when we work with uh with the

foundries, we tape out a test chip, but

we also need to make sure we package

them properly and the substrates are

built. And the whole package substrate

supply chain is still something that we

have to work collaboratively with. So,

we get these parts back to qualify them

on silicon.

>> I I think they they asked uh they needed

support for us, right? You know, they're

to achieve the best

PPA.

>> Mhm.

>> Uh performance, power, area, you know,

cost, right? And then the other things,

right? They want us to achieve the

first-time success. The time to market

becoming more and more critical, you

know, given the, you know, the

requirement of uh the annual uh design

cadence, right? It's getting more and

more important, and the L-chip is simply

uh execution machine. Yeah.

>> Uh not half of what they care about 20

to 30% of that 2 kW chip to come down.

So, it's a percentage of the power.

>> Yeah.

>> So, if you look at systems today, there

are two sort of systems in the AI space,

a heterogeneous system where a few

blocks are going in full throttle and

about, you know, 30 40% are

running at half the speed, and some of

them are fast asleep. And so, there's a

there is a complete uh

demarcation of power throttling going

on. So, customers want to optimize power

at each corner. So, if when a when a

chip [clears throat] is

completely at low voltage, they want to

roll lower the supply voltage and lower

the frequency. And when it's going at

high performance, they want to increase

the frequency and also manage the power

there.

So, in a heterogeneous system, the power

can vary based on the load balance. And

so, they want to optimize power there.

In a homogeneous system, there's huge

amount of currents coming in. So, not

only do they want to measure the current

which is coming in and because

everything is on, they want to throttle

the frequency in that case. So, they

want to balance performance with power

measurements that they've they've been

done. So, that apparently gives about a

20 to 30% power delta for these chips.

>> So,

huge that's to answer. And

we, at least at Cadence, you know, it

was probably um AlphaGo 2016, you know,

another fellow of course, yeah, Dennis

Hassabis,

where we we realized, "Look,

you know,

machine learning reinforcement learning

techniques, you know, what we call kind

of classic ML,

can actually solve computer science

problems that

we've been unable to solve for like 30

years. I mean, Cadence has been like 40

years in complex, you know, math plus

computer science. Every NP-complete

problem under the sun is in our

software. So, we realized, "Look, we can

actually use ML to, you know, to get

better better power, better performance,

better area, better runtime. We can

actually use it as just the next

algorithmic breakthrough."

And that's actually pretty pervasive

now, you know, you know, by my latest

count, we've had over a thousand

tape-outs using reinforcement learning

in back-end design to get better PPA.

Uh

now, then more recently, you know, in

the last few years since since ChatGPT,

of course,

now

the future isn't even to think about the

word tool.

>> Mhm.

>> It's to think about virtual engineer.

You're going to actually license a

virtual engineering capability cuz the

software has a human interface. You can

talk to the software and it will talk

back to you. And you can give it all the

inputs you give a human. So, that that

that's game changing. Now, of course, I

think that that hasn't happened yet.

>> Yeah.

>> Um but, to the point we were just

talking,

if we want to keep making more and more

chips that are more and more complex,

faster and faster, like I I forgot you

know, we think we could have a trillion

transistors inside a package by end of

the decade. So, you want to do a

trillion transistors, and you want to

tape out every 6 months,

you're going to need to have a the head

count doesn't exist. The only way is one

real human

needs to have, you know, an army of 10

or 100 virtual humans working for them.

So, that's kind of the cadence

longer-term vision.

>> Actually, a a lot of what is called

collaboration with partners. Like, I

mean, for example, with TSMC, we have

kind of showcased how AI can be used to

do like metal scheme exploration, which

is a very important step of the DTCO

process, and several custom our joint

customers are doing things like that to

get the best metal stack for their

particular design.

I think the work that we have done on

co-packaged optics, where we have

essentially connected AI with the

exploration steps of co-packaged optics,

that's a way to accelerate and improve

the results of the coop flow. So, I

think the partner partnership plays an

integral role, because that's how we are

solving the high-value problems of the

industry. But, then there is also a lot

of core technology, like our

reinforcement learning engine, which we

pioneered, really has impacted design

and verification and analog in a very

fundamental way. Similarly, with the

work we're doing with agents and agentic

workflows, again, you know, we are

expecting that essentially our Synopsys

EDA agents are working alongside human

engineers, and essentially a human

engineer can delegate significant chunks

of work to a Synopsys EDA agent.

>> The vision of Cadence longer-term is to

move beyond the idea of a tool to

actually

giving you a virtual silicon capability,

[clears throat] a a virtual human

resource.

Uh I'd say the second thing is that we

are not only about the chip. Right, that

that as I described that direction, so

we have moved from chip to package to

board to rack level to the whole, you

know, end-to-end

system that our customers are

increasingly engaging with us on. So

>> So in terms of advanced technology, we

are quite excited about

HBM, high-bandwidth memory. Now that

it's using a TSMC logic process, the

bandwidth has increased, the power has

also gone up with it.

So just looking at memories, you're

going from HBM to from three to four,

and now we're going to a custom HBM.

We're also looking at advancement in 3D,

right? Basically stacking one technology

one process technology on top of the

other.

Same story to try and add more compute.

Moving forward, we are looking at

developing IVRs, integrated voltage

regulators for vertical power delivery,

and also on CPO. So this is another

thing we are very excited about.

One last thing to mention would be SOW,

system on wafer. This is where This is

what we think is really exciting because

you can fit almost four quad racks on a

switch on a wafer.

>> Mhm.

>> So gate all around is 2 nanometer, and

this is should we have a working silicon

on that. So

in gate all around the customer problems

have become more towards power and

performance in common in conjunction. So

what we look for is we have to build

these analog functions in a different

way.

What you could do in .18 doesn't apply

in FinFET. What you do in FinFET doesn't

quite apply in gate all around because

the voltage levels have changed. You

still have You now have one transistor

with one core voltage to

build all your analog functions. So all

these intermediate analog voltages which

need to be generated have to have a

different philosophy of circuit

components,

and also how How you

manage bomb costs without having these

external reference voltages and external

pins that customers may need? So, from a

fundamental design point of view, it's

quite different going from across each

technology. Uh and we've sort of got to

the gate all around era by just doing

good circuit design.

>> Uh

uh how does the ecosystem need to evolve

as we're moving into, you know, this new

very advanced, very uh very advanced

process, very advanced packaging, and

all these little chiplets running

around? What happens to happen at the

ecosystem level to accept what

>> At an ecosystem level, you need more

collaboration. You need more partner

partners to jump in because at the end

of the day, even TSMC cannot handle all

of this, right? So, again, going back to

the OIP, I think this is an excellent uh

forum and platform for multiple

ecosystem partners to jump in.

>> So, after spending a full day with these

six companies, you begin to see how much

the quiet coordination holds the

industry together.

There is no single roadmap or central

authority directing progress. Even TSMC

can't dictate the direction of the

industry.

What keeps it moving is a network of

people and companies constantly talking

to one another, adjusting, and finding

alignment as technology shifts beneath

them. Semiconductors are unusual in that

sense. The companies compete hard, but

they also depend on one another more

than they would ever like to admit in

public.

A design house cannot move forward

unless the EDA tools are stable. IP

vendors need accurate foundry data to

validate their blocks.

At the foundry, it depends on those same

partners to help define the limits of

each new generation.

Every part of the system leans on all

the others, even when their commercial

interests do not perfectly align.

That balance can be fragile, but has to

be functional.

The people we spoke to today were clear

about how difficult it can be.

Collaboration requires constant work.

Sometimes it means helping a rival

because a smoother overall flow benefits

everyone in the long term.

It's not just generosity. It's the

practical reality of how progress

happens in a field where delays ripple

across the entire chain.

And there's also this human element side

to all of this that rarely gets seen.

Behind every new chip are relationships

built over years, often tested under

pressure. Trust grows through shared

problem-solving, through missed

deadlines and recovered schedules,

through the understanding that someone

will pick up the phone when you need

them to.

Those relationships are as essential as

the tools and IP that underpin them.

The OIP makes that structure visible for

a brief moment. It's where design tools,

packaging flows, and IP roadmaps meet

before new silicon ever exists.

It shows how coordination itself has

become some kind of engineering

discipline, one that requires just as

much skill and precision as the

technology being developed.

That's what ties all these conversations

together.

Every company we visited contributes

something different, yet they are

solving parts of the larger problem.

Each one has to stay in sync with the

others if the entire system is to keep

pace with its own ambitions.

So, on that end, that is what the

semiconductor ecosystem has become.

It's a living framework that evolves

alongside the technology, adapting and

reshaping itself every generation.

Progress depends on that framework

holding steady even as the challenges

grow.

The day and a bit I spent across these

six companies showed that coordination,

but quietly over time, but it's what

truly keeps the industry moving forward.